This invention relates, in general, to semiconductor devices, and more particularly, to semiconductor devices having enhanced carrier mobility.
Metal oxide semiconductor field effect transistor (MOSFET) devices are well known and widely used in the electronics industry. The carrier mobility of a MOSFET device is an important parameter because of its direct influence on output current and switching performance. In standard MOSFET technology, the channel length and gate dielectric thickness are reduced to improve current drive and switching performance. However, reducing the gate dielectric thickness can compromise device performance because of the associated increase in intrinsic gate capacitance.
In silicon MOSFET devices, it has been shown that a buried channel region under compressive stress consisting of a silicon/germanium (Si.sub.1-x Ge.sub.x) alloy, bounded above and below by silicon regions, enhances hole carrier mobility in the channel region. This is because the holes are confined to the channel region by the potential energy offset between the surrounding silicon regions and the Si.sub.1-x Ge.sub.x channel region. Such strained devices are shown in U.S. Pat. No. 5,241,197 issued to Murakami et al., and U.S. Pat. No. 5,019,882 issued to Solomon et al.
Buried Si.sub.1-x Ge.sub.x channel devices have several disadvantages including increased alloy scattering in the channel region that degrades electron mobility, no favorable conduction band offset thus minimally enhanced electron mobility, no higher carrier velocities than silicon, and the need for large Ge concentrations to produce strain and thus enhanced mobility. Large Ge concentrations result in greatly reduced layer thicknesses and processing temperatures. The reduced processing temperatures adversely affect dopant activation and gate oxide processing.
Silicon devices with channel regions under a tensile stress are desirable because the tensile strain results in both hole and electron mobility enhancement and increased carrier velocity compared to silicon. One reported approach uses a strained silicon surface channel region with a relaxed Si.sub.0.7 Ge.sub.0.3 alloy layer below the silicon channel region and a Si.sub.1-x Ge.sub.x (X=5-30%) buffer layer below the Si.sub.0.7 Ge.sub.0.3 alloy layer. One advantage of this approach is the elimination of alloy scattering in the channel region. However, this approach has a disadvantage in that the strained channel layer is at the surface and is thus susceptible to surface scattering effects that reduce mobility. It is also susceptible to hot carrier degradation and noise problems. In addition, the approach requires alloy relaxing and buffering layers, which increases process complexity and costs.
Another reported approach uses a strained Si.sub.1-x Ge.sub.x channel layer formed on a relaxed Si.sub.1-y Ge.sub.y layer (where Y&gt;X) with a silicon layer above the strained Si.sub.1-x Ge.sub.x channel layer and a silicon layer below the relaxed Si.sub.1-y Ge.sub.y layer. This structure has several disadvantages including the migration of carriers out of the strained Si.sub.1-x Ge.sub.x channel layer into the relaxed Si.sub.1-y Ge.sub.y alloy layer thus reducing the enhanced mobility effect, greater alloy scattering effects because of the presence of germanium in the channel layer, and added process complexity because of multiple SiGe layers.
As is readily apparent, there exists a need for a MOSFET device that has enhanced electron and hole mobility, that is less susceptible to alloy scattering effects, that is less susceptible to surface scattering effects, and that does not require alloy relaxing and/or buffering layers.